#include <NandDrv.h>
#include <S3C2440addr.h>

#define GPF1_MASK (0x3 << 2)
#define GPF4_MASK (0x3 << 8)
#define GPF2_MASK (0x3 << 4)
#define GPF0_MASK (0x3 << 0)

#define GPF1_AS_INT (0x2 << 2)
#define GPF4_AS_INT (0x2 << 8)
#define GPF2_AS_INT (0x2 << 4)
#define GPF0_AS_INT (0x2 << 0)



void close_watch_dog() {
    rWTCON      = 0;
}


#define CLKDIVN (*(volatile unsigned long*)0x4c000014)
#define MPLLCON (*(volatile unsigned long*)0x4c000004)

void init_clock() {
    rLOCKTIME = 0xFFFFFFFF;

    CLKDIVN = 0x3; //FCKL:HCLK:PCLK = 1:2:4

    //set async bus mode
    __asm__ (
        "mrc p15,0,r1,c1,c0,0\n"
        "orr r1,r1,#0xc0000000\n"
        "mcr p15,0,r1,c1,c0,0\n"
    );

    /*
     *    FOUT = 2 * m * Fin / (p*2S), FVCO = 2 * m * Fin / p where: m=MDIV+8, p=PDIV+2, s=SDIV
     *    200MHz ≤ FCLK OUT ≤ 600MHz
     *    PDIV = 2, SDIV = 1, FOUT = 200MHz, Fin = 12MHz => MDIV = 58(0x3a)
     PLLCON   Bit      Description
     MDIV     [19:12]  Main divider control
     PDIV     [9:4]    Pre-divider control
     SDIV     [1:0]    Post divider control
     */
    MPLLCON = ((0x5c << 12) | (1 << 4) | 2);//0x5c012
}


void init_sdram() {
    int i = 0;
    unsigned long* pIt = (unsigned long*)0x48000000;
    unsigned long reg_value_arr[] = {
            0x22011110,
            0x700,
            0x700,
            0x700,
            0x700,
            0x700,
            0x700,
            0x00018005,
            0x00018005,
            0x008c04F4,
            0xB1,
            0x30,
            0x30
    };

    for(i = 0; i < 13; ++i) {
        *pIt = reg_value_arr[i];
        ++pIt;
    }
}



void copy_main_code_nand2sdram()
{
    unsigned int i;
    unsigned int start_addr = 0x1000;
    unsigned char * to = (unsigned char *)0x30000000;
    int size = 1024 * 1024;//1M
    rNF_Init();

    for(i = (start_addr >> 11); size > 0; ++i)
    {
        rLB_ReadPage(i, to);//i = 2,3
        size -= 2048;
        to += 2048;
    }
    return;
}

void init_irq() {
    rINTMSK     = 0xFFFFFFFF;
    rINTSUBMSK  = 0xFFFFFFFF;
}











